Samsung says the explosive growth of AI workloads will force the industry to rethink how memory is built and connected. At the Future of Memory and Storage (FMS) 2026 conference, the company unveiled a trio of next‑generation memory technologies designed to break through current limits in performance, power efficiency, and capacity.semiconductor.samsung+2

All three concepts share a common foundation: wafer bonding. This manufacturing technique joins two or more completed silicon wafers into a single, tightly integrated device. Instead of fabricating every component on one wafer, manufacturers build different parts separately—such as the memory cell array and the peripheral circuitry—then align and bond them with extreme precision.news.samsung+2

Wafer bonding matters because it is one of the few remaining paths to keep scaling semiconductors once traditional planar processes hit physical and economic walls. It enables much higher memory density in the same 2D footprint and allows each wafer to be produced using the optimal process node before being combined.news.samsung+1

The technique is already familiar in NAND flash, where memory cells are stacked vertically like floors in a high‑rise. First introduced in 2014 with 24‑layer NAND, the technology has since surpassed the 300‑layer mark. Samsung’s new announcements push this idea even further.

BV‑NAND: the centerpiece for AI storage

The headline product is BV‑NAND (Bonding V‑NAND), Samsung’s next‑generation flash architecture built on wafer bonding. The company showcased the industry’s first V10 BV‑NAND module with more than 400 layers, a milestone enabled by bonding the memory array and logic on separate wafers.news.samsung+2

According to Samsung, this approach boosts storage density by roughly 58% compared with the current V9 generation, while also improving read, write, and I/O performance and cutting power consumption. That makes BV‑NAND especially attractive for AI servers that rely on massive, fast, and energy‑efficient flash storage.news.samsung+2

zHBM and zNAND‑O: reimagining memory placement

Beyond storage, Samsung outlined two longer‑term concepts that could reshape AI system architecture.

zNAND‑O targets edge AI devices. It uses TSV (through‑silicon via) processes to vertically stack NAND in compact 4‑ or 8‑layer configurations, trading some capacity for very low latency and high spatial efficiency—ideal for on‑device inference where space and power are at a premium

zHBM proposes stacking HBM (high‑bandwidth memory) directly on top of the AI accelerator instead of placing it beside the processor on the same package. By shortening the distance data must travel, Samsung expects significantly higher bandwidth, lower latency, and reduced power and heat. Early estimates suggest up to 8× the performance of HBM5, 10× higher memory density, 3× better energy efficiency, and over 50% lower thermal resistance when combined with advanced wafer bonding.osp+2

Why this matters for AI infrastructure

Together, these technologies signal a shift from “more of the same” scaling to 3D‑first memory architectures. As AI models grow and data centers demand ever more bandwidth and capacity, simply adding more chips side‑by‑side is becoming inefficient. Vertical integration—stacking memory closer to compute and using wafer bonding to bypass single‑wafer limits—offers a path forward.semiconductor.samsung+2

For now, V10 BV‑NAND is the most concrete outcome, with zHBM and zNAND‑O presented as concept models. But if Samsung’s projections hold, these designs could define the next generation of AI‑optimized memory and storage systems